The present invention relates in general to packaging of a semiconductor device, and more specifically to low thermal resistance packaging with improved reliability.
Semiconductor devices, such as power switching devices and very high frequency digital devices (e.g., microprocessors with many transistors), continue to generate excessive thermal energy. In measuring thermal performance of a semiconductor device, such as a power MOSFET device, the device is typically characterized by its ability to dissipate internally generated heat and its equivalent operational drain to source on resistance (or RDSON).
While silicon process technology has advanced significantly in recent years, semiconductor package technology remains essentially unchanged. Epoxy or solder die attach along with aluminum or gold wire interconnects is still employed for a great majority of device packages. FIG. 1 illustrates a conventional package and its wiring for an exemplary power MOSFET 100. Wire bonds 104 connect the source and gate terminals of the semiconductor die 108 to electrical conductors, such as conductive single trace comprising copper or the like. Die 108 and wire bonds 104 are encapsulated in body 102 made of, for example, molding compound suitable for power MOSFET applications.
For the exemplary power MOSFET 100, backside 110 of die 108 provides a drain connection. Die 108 is attached to a metal land 112 on a substrate such as a printed circuit board (PCB) 122 using die attach material such as solder that may be thermally and/or electrically conductive. Metal land 112 not only provides an electrical conduit to drain conductor 116 by way of one or more conductive vias 114, it also acts as a heat sink by providing a mechanism to dissipate heat within PCB 122.
Conventional packaging techniques such as that depicted in FIG. 1 tend to perform relatively poorly in terms of device on-resistance as well as thermal resistance. For example, the wire bonds add relatively large resistance to the otherwise low on-state resistance of the high current MOSFET. Also, placement of the wires on the terminals of the device is constrained by wire length, bond size relative to the bond pad area, and vertical clearance inside the molded body, among other factors. Even the relatively thick top metalization at each terminal adds resistance and is compounded by wire interconnect placement limitations. Further, die attach solder 112 adds to the thermal resistance of the device increasing the amount of heat that is generated internally when large current flow through the drain terminal. Another drawback of this type of package relates to the cost-prohibitive and difficult aspects of reworking such a packaged semiconductor device due, in part, to the encapsulated nature of the packaging. Other drawbacks include non-optimized and relatively think package profiles due to loop heights of wires used with conventional wire-bonding technology.
An improved semiconductor packaging technique allows the semiconductor die to protrude from the semiconductor package. The package is configured such that the backside of the die directly contacts a heat sink residing on a PCB. For this type of package, the die is typically singulated and prepared by grinding, lapping, sawing and other mechanical operations. Mechanical operations used to perform die preparation and processing can introduce “micro-cracks” into the die, especially at the die edge. This type of defect can reduce the strength, or “fracture toughness,” of the die by as much as 70% if the die is made of, for example, silicon. The edge thus becomes a weakened zone adversely affecting the reliability of the die. In addition, the die edge with such defects may provide a path for moisture penetration between the die and the molding compound of the body. This subjects the device to corrosion and other environmental factors that further decrease the reliability of the device. Also, the metal-semiconductor contact providing the drain contact is close to the soldering surface of the package. The disadvantage of the contact being close to the soldering surface is that delamination of the metal from the silicon is more likely during the soldering process when flux and molten solder can come in contact with the edge of the metal-silicon contact or interface.
There is a need for improved packaging techniques that minimize electrical as well as thermal resistance for semiconductor devices, such as power MOSFETs, while improving reliability and manufacturability.